1. Field of the Invention
The present invention relates to an ESD protection circuit and particularly to a gate-coupled MOSFET ESD protection circuit.
2. Description of the Prior Art
In a Human-Body-Model ESD transient, a 100PF capacitor is first charged up to an ESD pulse voltage, and then discharged through a 1.5-kohm resistor onto an IC pin. Typically, a pulse voltage level of 2 KV is used to qualify an IC package. The initial peak current is roughly 1.2 A with a rise time of approximately 10 nsec. For integrated circuit packages, the VDD-to-VSS capacitance is typically larger than 1 NF. If the ESD energy is directly absorbed by the power bus (for ESD stress of VDD pin to VSS pin), or indirectly absorbed by the power bus (for example, positive ESD stress on an input or I/O pin that has a pull up device such as p+/n well or PMOSFET), then the voltage-rising rate inside an IC can reach 1 to 2 volt per nano-second for a Human-Body-Model ESD pulse at 2 to 3 KV level.
Transistors, such as grounded-gate NMOS (GGNMOS), field-oxide device, or output buffer transistors, have been commonly used as primary ESD protection elements for integrated circuits.
For ESD protection of an IC pin or a power bus, GGNMOS can be used as the primary ESD protection. The drain of the NMOS transistor is connected to VDD or the IC pin, while the source of the NMOS transistor is connected to VSS. The gate is either grounded (GGNMOS), or coupled to VDD by a capacitor and to VSS by a resistor (GCNMOS or Gate-Coupled NMOS).
ESD Voltage Clamping Device
One well known ESD protection circuit involves the use of a transistor controlled by a resistance-capacitance (RC) circuit for shunting the flow of ESD current between the protected bond pad and a power supply pad (e.g., VSS).
FIG. 1 shows a conventional RC-triggered active MOSFET ESD clamp circuit. The clamp circuit provides a current shunt to protect internal circuit for a VDD-to-VSS positive voltage ESD event. The inverter 11 composed of the transistors N1 and P1 inverts a voltage on a node E to an output voltage on a node G, which keeps the transistor N1 conductive for a period of time as determined by the RC time constant (R1C1). It is critical that this RC time constant is long enough to exceed the maximum expected duration of an ESD event, typically in the range of 50 nanoseconds to a few hundred nanoseconds, while short enough to avoid false triggering of the clamp circuit during normal ramp-up of the VDD power bus, typically a few milliseconds. During normal operation of the IC, with a constant VDD power supply level, the transistor N1 is biased in a nonconductive state due to the resistor R1 pulling node E at High and node G at Low.
The described voltage-clamping ESD protection device can be used to protect between VDD and VSS power supply rails. However, certain concerns are that (i) the device size is typically very large, e.g., with a number of power-bus-clamp NMOSFETs having a total channel width of 4000 to 10,000 m; and (ii) the inverter 11 amplifies the power-bus noise through the node E, causing undesirable leakage current at N2 during circuit operation.
ESD Protection by Avalanche Breakdown
Another well-known ESD protection method is based on the avalanche breakdown and snapback of a MOSFET device. At the beginning, the high electric field at the drain junction causes impact ionization with generation of both minority and majority carriers. The minority carriers are collected at the drain (anode), while the majority carriers flow toward the substrate or p-well contact (cathode) causing a local potential buildup in the p-well. When the local substrate potential is 0.8V higher than the adjacent n+ source potential, the source junction becomes forward biased. The forward biased source junction injects minority carriers into the p-well. Some of those injected minority carriers are recombined in the substrate while the rest of them reach the drain junction to further enhance the impact ionization. As a continuous loop, the MOSFET enters a low impedance (snapback) state to conduct large amounts of ESD current.
It is of great advantage to reduce the triggering voltage of a MOSFET during an ESD event. The ESD protection can occur sooner, and the transient voltage imposed on the I/O and internal circuit can be lower, for better overall ESD protection.
FIG. 2 shows a conventional gate-coupled ESD protection circuit. The RC time constant is chosen such that the node G is at about 1 to 2 volts (or around 0.7V to 2V) during an ESD transient for reducing ESD triggering voltage for avalanche breakdown and snapback.
For GGNMOS or GCNMOS, because the conduction of ESD current is through the drain/substrate/source (npn) bipolar junction, it can conduct a large ESD current with a smaller MOSFET when compared to a voltage clamping ESD protection device, and for power bus ESD protection, typically one with a total channel width of, for example, 600 to 1200 m may provide sufficient ESD protection.
However, for a GCNMOS, the selection of the RC time constant for optimized ESD triggering duration and the transient voltage on the node G for different ESD pulse levels may sometimes impose some difficulty.